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U635H256
PowerStore 32K x 8 nvSRAM
Features Description
The U635H256 has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as an ordinary static RAM. In nonvolatile operation, data is transferred in parallel from SRAM to EEPROM or from EEPROM to SRAM. In this mode SRAM functions are disabled. The U635H256 is a fast static RAM (25, 35, 45 ns), with a nonvolatile electrically erasable PROM (EEPROM) element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in EEPROM. Data transfers from the SRAM to the EEPROM (the STORE operation) take place automatically upon power down using charge stored in system capacitance. Transfers from the EEPROM to the SRAM (the RECALL operation) take place automatically on power up. The U635H256 combines the high performance and ease of use of a fast SRAM with nonvolatile data integrity. STORE cycles also may be initiated under user control via a software sequence. Once a STORE cycle is initiated, further input or output are disabled until the cycle is completed. Because a sequence of addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence or the sequence will be aborted. RECALL cycles may also be initiated by a software sequence. Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times. The U635H256 is pin compatible with standard SRAMs.
F F F F F F F F F F F F F F F F F
High-performance CMOS nonvolatile static RAM 32768 x 8 bits 25, 35 and 45 ns Access Times 10, 15 and 20 ns Output Enable Access Times ICC = 15 mA at 200 ns Cycle Time Automatic STORE to EEPROM on Power Down using system capacitance Software initiated STORE Automatic STORE Timing 105 STORE cycles to EEPROM 10 years data retention in EEPROM Automatic RECALL on Power Up Software RECALL Initiation Unlimited RECALL cycles from EEPROM Single 5 V 10 % Operation Operating temperature range: 0 to 70 C -40 to 85 C CECC 90000 Quality Standard ESD characterization according MIL STD 883C M3015.7-HB (classification see IC Code Numbers) Packages: PDIP28 (300 mil) PDIP28 (600 mil) SOP28 (330 mil)
Pin Configuration
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 PDIP 22 SOP 21 20 19 18 17 16 15 VCC W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
Pin Description
Signal Name
A0 - A14 DQ0 - DQ7 E G W VCC VSS
Signal Description
Address Inputs Data In/Out Chip Enable Output Enable Write Enable Power Supply Voltage Ground
Top View
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U635H256
Block Diagram
EEPROM Array 512 x (64 x 8) A5 A6 A7 A8 A9 A11 A12 A13 A14 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 E W Input Buffers STORE Row Decoder SRAM Array 512 Rows x 64 x 8 Columns
Store/ Recall Control
VCC VSS
RECALL
Power Control
VCC
Column I/O Column Decoder
Software Detect
A0 - A13
A0 A1 A2 A3 A4 A10
G
Truth Table forSRAM Operations Operating Mode Standby/not selected Internal Read Read Write * H or L Characteristics
All voltages are referenced to V SS = 0 V (ground). All characteristics are valid in the power supply voltage range and in the operating temperature range specified. Dynamic measurements are based on a rise and fall time of 5 ns, measured between 10 % and 90 % of V I, as well as input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V, with the exception of the t dis-times and t en-times, in which cases transition is measured 200 mV from steady-state voltage.
E H L L L
W * H H L
G * H L *
DQ0 - DQ7 High-Z High-Z Data Outputs Low-Z Data Inputs High-Z
Absolute Maximum Ratingsa Power Supply Voltage Input Voltage Output Voltage Power Dissipation Operating Temperature Storage Temperature
a:
Symbol VCC VI VO PD C-Type K-Type Ta Tstg
Min. -0.5 -0.3 -0.3
Max. 7 VCC+0.5 VCC+0.5 1
Unit V V V W C C C
0 -40 -65
70 85 150
Stresses greater than those listed under Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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U635H256
Recommended Operating Conditions Power Supply Voltage Input Low Voltage Input High Voltage Symbol VCC VIL VIH -2 V at Pulse Width 10 ns permitted Conditions Min. 4.5 -0.3 2.2 Max. 5.5 0.8 VCC+0.3 Unit V V V
C-Type DC Characteristics Operating Supply Currentb Symbol ICC1 VCC VIL VIH tc tc tc Average Supply Current duringc STORE ICC2 VCC E W VIL VIH VCC W VIL VIH VCC VIL VIH VCC E tc tc tc Standby Supply Curentd (Stable CMOS Input Levels) ICC(SB) VCC E VIL VIH Conditions Min. = 5.5 V = 0.8 V = 2.2 V = 25 ns = 35 ns = 45 ns = 5.5 V 0.2 V VCC-0.2 V 0.2 V VCC-0.2 V = 5.5 V VCC-0.2 V 0.2 V VCC-0.2 V = 4.5 V = 0.2 V VCC-0.2 V = 5.5 V = VIH = 25 ns = 35 ns = 45 ns = 5.5 V VCC-0.2 V 0.2 V VCC-0.2 V 40 36 33 3 95 75 65 6 Max.
K-Type Unit Min. Max.
100 80 70 7
mA mA mA mA
Operating Supply Currentb at tcR = 200 ns (Cycling CMOS Input Levels) Average Supply Current duringc PowerStore Cycle Standby Supply Currentd (Cycling TTL Input Levels)
ICC3
15
15
mA
ICC4
4
4
mA
ICC(SB)1
42 38 35 3
mA mA mA mA
ICC1 and ICC3 are depedent on output loading and cycle rate. The specified values are obtained with outputs unloaded. The current ICC1 is measured for WRITE/READ - ratio of 1/2. c: ICC2 and ICC4 are the average currents required for the duration of the respective STORE cycles. d: Bringing E VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION table. The current ICC(SB)1 is measured for WRITE/READ - ratio of 1/2.
b:
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U635H256
C-Type DC Characteristics Symbol VCC IOH IOL VCC VOH VOL VCC High Low Output Leakage Current High at Three-State- Output Low at Three-State- Output IOHZ IOLZ IIH IIL VIH VIL VCC VOH VOL Conditions Min. Output High Voltage Output Low Voltage Output High Current Output Low Current Input Leakage Current VOH VOL IOH IOL = 4.5 V =-4 mA = 8 mA = 4.5 V = 2.4 V = 0.4 V = 5.5 V = 5.5 V = 0V = 5.5 V = 5.5 V = 0V 1 -1 -1 1 A A 1 -1 -1 1 A A 2.4 0.4 -4 8 8 Max. Min. 2.4 0.4 -4 Max. V V mA mA K-Type Unit
SRAM MEMORY OPERATIONS Symbol Alt. tAVAV Validg tAVQV tELQV tGLQV tEHQZ tGHQZ tELQX tGLQX tAXQX tELICCH tEHICCL IEC tcR ta(A) ta(E) ta(G) tdis(E) tdis(G) ten(E) ten(G) tv(A) tPU tPD 5 0 3 0 25 Min. 25 25 25 10 10 10 5 0 3 0 35 25 Max. Min. 35 35 35 15 13 13 5 0 3 0 45 35 Max. 45 Unit Min. 45 45 45 20 15 15 Max. ns ns ns ns ns ns ns ns ns ns ns
No. 1 2 3 4 5 6 7 8 9
Switching Characteristics Read Cycle Read Cycle Timef Address Access Time to Data
Chip Enable Access Time to Data Valid Output Enable Access Time to Data Valid E HIGH to Output in High-Z h
h
G HIGH to Output in High-Z E LOW to Output in Low-Z G LOW to Output in Low-Z
Output Hold Time after Address Change Activee Standbyd, e
10 Chip Enable to Power 11 Chip Disable to Power
e: f: g: h:
Parameter guaranteed but not tested. Device is continuously selected with E and G both Low. Address valid prior to or coincident with E transition LOW. Measured 200 mV from steady state output voltage.
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U635H256
Read Cycle 1: Ai-controlled (during Read cycle: E = G = VIL, W = VIH)f
1 tcR
Ai
Address Valid 2 ta(A)
DQi
Output
Previous Data Valid 9 tv(A )
AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA
Output Data Valid
Read Cycle 2: G-, E-controlled (during Read cycle: W = VIH)g
1 tcR
Ai
Address Valid 2 ta(A) 3 ta(E) 7 ten(E)
E G DQi
Output High Impedance
5 tdis(E)
4 ta(G) 6 tdis(G)
11 tPD
8 ten(G) 10 tPU
AAAAAAAAAAAA Output Data AAAAAAAAAAAA AAAAAAAAAAAA Valid AAAAAAAAAAAA
ICC
ACTIVE STANDBY
No.
Switching Characteristics Write Cycle
Symbol Alt. #1 Alt. #2 tAVAV tWLWH tWLEH tAVWL tAVWH tELWH tELEH tDVWH tWHDX tWHAX tWLQZ tWHQX tDVEH tEHDX tEHAX tAVEL tAVEH tAVAV IEC tcW tw(W) tsu(W) tsu(A) tsu(A-WH) tsu(E) tw(E) tsu(D) th(D) th(A) tdis(W) ten(W) 5
25
35
45 Unit
Min. Max. Min. Max. Min. Max. 25 20 20 0 20 20 20 10 0 0 10 5 35 25 25 0 25 25 25 12 0 0 13 5 45 30 30 0 30 30 30 15 0 0 15 ns ns ns ns ns ns ns ns ns ns ns ns
12 Write Cycle Time 13 Write Pulse Width 14 Write Pulse Width Setup Time 15 Address Setup Time 16 Address Valid to End of Write 17 Chip Enable Setup Time 18 Chip Enable to End of Write 19 Data Setup Time to End of Write 20 Data Hold Time after End of Write 21 Address Hold after End of Write 22 W LOW to Output in High-Zh, i
23 W HIGH to Output in Low-Z
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U635H256
Write Cycle #1: W-controlledj
12 tcW
Ai
Address Valid 17 tsu(E) 21 th(A)
E
AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAA AAAAAAA AAAAAAA 15 AAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
13
16 tsu(A-WH)
W
t w(W)
tsu(A)
19 tsu(D) Input Data Valid 22 tdis(W)
20 th(D)
DQi
Input
DQi
Output Previous Data
23 ten(W) High Impedance
AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA
Write Cycle #2: E-controlled j
12 tcW
Ai
15 tsu(A )
Address Valid 18 tw(E) 21 th(A)
E W
AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA
14 tsu(W) 19 tsu(D)
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
20 th(D) Input Data Valid High Impedance
DQi
Input
DQi
Output
AAAAAAAAAAAA AAAAAAAAAAAA undefined AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA
AAAAAAAAAAAAA AAAAAAAAAAAAA L- to H-level AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA
AAAAAAAAAAAAA AAAAAAAAAAAAA H- to L-level AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA
i: j:
If W is low and when E goes low, the outputs remain in the high impedance state. E or W must be VIH during address transition.
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U635H256
NONVOLATILE MEMORY OPERATIONS MODE SELECTION A13 - A0 (hex) X X X 0E38 31C7 03E0 3C1F 303F 0FC0 0E38 31C7 03E0 3C1F 303F 0C63
E H L L L
W X H L H
Mode Not Selected Read SRAM Write SRAM Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL
I/O Output High Z Output Data Input Data Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z
Power Standby Active Active Active
Notes
m
k, l k, l k, l k, l k, l k, l k, l k, l k, l k, l k, l k, l
L
H
Active
k: The six consecutive addresses must be in order listed. W must be high during all six consecutive cycles. See STORE cycle and RECALL cycle tables and diagrams for further details. The following six-address sequence is used for testing purposes and should not be used: 0E38, 31C7, 03E0, 3C1F, 303F, 339C. l: While there are 15 addresses on the U635H256, only the lower 14 are used to control software modes. Activation of nonvolatile cycles does not depend on the state of G. m: I/O state assumes that G VIL.
No.
PowerStore Power Up RECALL
Symbol Conditions Alt. tRESTORE the power supply voltage must be stay above 3.6 V for at least 10 ms after the start of the STORE operation 1 4.0 4.5 IEC 650 s Min. Max. Unit
24 Power Up RECALL Durationn
25 STORE Cycle Durationf, e
tPDSTORE
10
ms
26
Time allowed to Complete SRAM Cyclef Low Voltage Trigger Level
tDELAY VSWITCH
s V
n:
tRESTORE starts from the time VCC rises above VSWI TCH .
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U635H256
PowerStore and automatic Power Up RECALL
VCC 5.0 V AAAA VSWITCH A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A
t
PowerStore
tPDSTOREp
24 24
Power Up RECALL W
tRESTORE
tRESTORE tDELAYp
DQi POWER UP BROWN OUT NO STORE RECALL (NO SRAM WRITES) BROWN OUT PowerStore
No.
Software Controlled STORE/ RECALL Cyclek, o
Symbol Alt. tAVAV tELQZ tELQXS tELQXR tAVELN tELEHN tEHAXN IEC tcR tdis(E)SR td(E)S td(E)R tsu(A)SR tw(E)SR th(A)SR 0 20 0
25
35
45 Unit
Min. Max. Min. Max. Min. Max. 25 600 10 20 0 25 0 35 600 10 20 0 30 0 45 600 10 20 ns ns ms s ns ns ns
27 STORE/RECALL Initiation Time 28 Chip Enable to Output Inactivep 29 STORE Cycle Timeq 30 RECALL Cycle Timer 31 Address Setup to Chip Enables 32 Chip Enable Pulse Widths, t 33 Chip Disable to Address Changes
o: p: q: r: s: t:
The software sequence is clocked with E controlled READs. Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs. Note that STORE cycles (but not RECALL) are aborted by VCC < VSWI TCH (STORE inhibit). An automatic RECALL also takes place at power up, starting when V CC exceeds VSWITCH and takes t RESTORE . VCC must not drop below VSWITCH once it has been exceeded for the RECALL to function properly. Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence. If the Chip Enable Pulse Width is less than t a(E) (see Read Cycle) but greater than or equal tw(E)SR , than the data may not be valid at the end of the low pulse, however the STORE or RECALL will still be initiated.
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U635H256
SOFTWARE CONTROLLED STORE/RECALL CYCLEt, u, v (E = HIGH after STORE initiation)
AAAAAAAAAAA AAAAAAAAAAA Ai AAAAAAAAAAA AAAAAAAAAAA
27 tcR ADDRESS 1 27 tcR ADDRESS 6
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
29 / 30 td(E)S / td(E)R
E
31 tsu(A)SR
32 tw(E)SR
33 th(A)SR
DQi
Output
High Impedance
VALID
VALID 28 tdis(E)SR
AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA
SOFTWARE CONTROLLED STORE/RECALL CYCLEt, u, v, w (E = LOW after STORE initiation)
29 tcR ADDRESS 1 34 tw(E)SR ADDRESS 6
Ai AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA E
AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA
35 th(A)SR AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
33 tsu(A)SR High Impedance
35 th(A)SR
33 tsu(A )SR
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA
31 / 32 td(E)S / td(E)R VALID 30 t dis(E)SR
DQi
Output
VALID
u:
v:
W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines wheter the U635H256 performs a STORE or RECALL. E must be used to clock in the address sequence for the Software controlled STORE and RECALL cycles.
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U635H256
Test Configuration for Functional Check
5V
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14
VCCX
Input level according to the
relevant test measurement
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
VIH
VIL
ment of all 8 output pins
Simultaneous measure-
480
VO
E W G
30 pF w 255
VSS
w: In measurement of tdis-times and ten-times the capacitance is 5 pF. x: Between VCC and VSS must be connected a high frequency bypass capacitor 0.1 F to avoid disturbances.
Capacitancee Input Capacitance Output Capacitance
Conditions VCC VI f Ta = 5.0 V = VSS = 1 MHz = 25 C
Symbol CI CO
Min.
Max. 8 7
Unit pF pF
All Pins not under test must be connected with ground by capacitors.
IC Code Numbers Example U635H256 Type ESD Class B > 1000 V y C > 500 V Package D = PDIP (300 mil) D1 = PDIP (600 mil) S = SOP (330 mil) Operating Temperature Range C = 0 to 70 C K = -40 to 85 C C D C 25
Access Time 25 = 25 ns 35 = 35 ns (on special request) 45 = 45 ns (on special request)
The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year, and the last 2 digits the calendar week.
y: ESD protection > 1000 V and 2000 V under development
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U635H256
Device Operation The U635H256 has two separate modes of operation: SRAM mode and nonvolatile mode. The memory operates in SRAM mode as a standard fast static RAM. Data is transferred in nonvolatile mode from SRAM to EEPROM (the STORE operation) or from EEPROM to SRAM (the RECALL operation). In this mode SRAM functions are disabled. STORE cycles may be initiated under user control via a software sequence and are also automatically initiated when the power supply voltage level of the chip falls below VSWITCH. RECALL operations are automatically initiated upon power up and may also occur when the VCC rises above VSWITCH, after a low power condition. RECALL cycles may also be initiated by a software sequence. SRAM READ SOFTWARE NONVOLATILE STORE The U635H256 performs a READ cycle whenever E and G are LOW and W is HIGH. The address specified on pins A0 - A14 determines which of the 32768 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tcR. If the READ is initiated by E or G, the outputs will be valid at ta(E) or at ta(G), whichever is later. The data outputs will repeatedly respond to address changes within the tcR access time without the need for transition on any control input pins, and will remain valid until another address change or until E or G is brought HIGH or W is brought LOW. SRAM WRITE A WRITE cycle is performed whenever E and W are LOW. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes HIGH at the end of the cycle. The data on pins DQ0 - 7 will be written into the memory if it is valid tsu(D) before the end of a W controlled WRITE or tsu(D) before the end of an E controlled WRITE. It is recommended that G is kept HIGH during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left LOW, internal circuitry will turn off the output buffers tdis (W) after W goes LOW. AUTOMATIC STORE The U635H256 uses the intrinsic system capacitance to perform an automatic STORE on power down. As long as the system power supply take at least tPDSTORE to decay from VSWITCH down to 3.6 V the U635H256 will safely and automatically STORE the SRAM data in EEPROM on power down. In order to prevent unneeded STORE operations, automatic STORE will be ignored unless at least one The U635H256 software controlled STORE cycle is initiated by executing sequential READ cycles from six specific address locations. By relying on READ cycles only, the U635H256 implements nonvolatile operation while remaining compatible with standard 32K x 8 SRAMs. During the STORE cycle, an erase of the previous nonvolatile data is performed first, followed by a parallel programming of all the nonvolatile elements. Once a STORE cycle is initiated, further inputs and outputs are disabled until the cycle is completed. Because a sequence of addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence or the sequence will be aborted. To initiate the STORE cycle the following READ sequence must be performed: 1. 2. 3. 4. 5. 6. Read addresses Read addresses Read addresses Read addresses Read addresses Read addresses 0E38 31C7 03E0 3C1F 303F 0FC0 (hex) (hex) (hex) (hex) (hex) (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE Cycle WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether or not a WRITE operation has taken place. AUTOMATIC RECALL During power up, an automatic RECALL takes place. At a low power condition (power supply voltage < VSWITCH) an internal RECALL request may be latched. As soon as power supply voltage exceeds the sense voltage of VSWITCH, a requested RECALL cycle will automatically be initiated and will take tRESTORE to complete. If the U635H256 is in a WRITE state at the end of power up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10 k resistor should be connected between W and power supply voltage.
Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence, although it is not necessary that G be LOW for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation.
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U635H256
SOFTWARE NONVOLATILE RECALL A RECALL cycle of the EEPROM data into the SRAM is initiated with a sequence of READ operations in a manner similar to the STORE initiation. To initiate the RECALL cycle the following sequence of READ operations must be performed: 1. 2. 3. 4. 5. 6. Read addresses Read addresses Read addresses Read addresses Read addresses Read addresses 0E38 31C7 03E0 3C1F 303F 0C63 (hex) (hex) (hex) (hex) (hex) (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL Cycle HARDWARE PROTECTION The U635H256 offers hardware protection against inadvertent STORE operation through VCC Sense. When VCC < VSWITCH all software STORE operations will be inhibited. LOW AVERAGE ACTIVE POWER The U635H256 has been designed to draw significantly less power when E is LOW (chip enabled) but the access cycle time is longer than 55 ns. When E is HIGH the chip consumes only standby current. The overall average current drawn by the part depends on the following items: 1. CMOS or TTL input levels 2. the time during which the chip is disabled (E HIGH) 3. the cycle time for accesses (E LOW) 4. the ratio of READs to WRITEs 5. the operating temperature 6. the VCC level
Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. After td(E)R cycle time the SRAM will once again be ready for READ and WRITE operations.The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times.
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December 12, 1997
Memory Products 1998 PowerStore 32K x 8 nvSRAM U635H256
LIFE SUPPORT POLICY ZMD products are not designed, intended, or authorized for use as components in systems intend for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ZMD product could create a situation where personal injury or death may occur. Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.
The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved.
Zentrum Mikroelektronik Dresden GmbH Grenzstrae 28 * D-01109 Dresden * P. O. B. 80 01 34 * D-01101 Dresden * Germany Phone: +49 351 88 22-3 06 * Fax: +49 351 88 22-3 37 * Email: sales@zmd.de Internet Web Site: http://www.zmd.de

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